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<a href="#groups">API Reference</a> &#124;
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<a href="#define-members">Macros</a>  </div>
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<div class="title">Macros<div class="ingroups"><a class="el" href="group__group__sysclk.html">SysClk       (System Clock)</a></div></div>  </div>
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<a name="details" id="details"></a><h2 class="groupheader">General Description</h2>
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API Reference</h2></td></tr>
<tr class="memitem:group__group__sysclk__ecostatus"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__ecostatus.html">ECO status</a></td></tr>
<tr class="memdesc:group__group__sysclk__ecostatus"><td class="mdescLeft">&#160;</td><td class="mdescRight">Constants used for expressing ECO status. <br /></td></tr>
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Data Structures</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__clk__eco__config__t.html">cy_stc_clk_eco_config_t</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">structure for Cy_SysClk_EcoManualConfigure function parameters  <a href="structcy__stc__clk__eco__config__t.html#details">More...</a><br /></td></tr>
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Macros</h2></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__macros.html#ga13952b966a0787ea58ca78dc5916d0df">CY_SYSCLK_DRV_VERSION_MAJOR</a>&#160;&#160;&#160;3</td></tr>
<tr class="memdesc:ga13952b966a0787ea58ca78dc5916d0df"><td class="mdescLeft">&#160;</td><td class="mdescRight">Driver major version. <br /></td></tr>
<tr class="separator:ga13952b966a0787ea58ca78dc5916d0df"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae92890ad068051d74200a1ffb67b74e2"><td class="memItemLeft" align="right" valign="top"><a id="gae92890ad068051d74200a1ffb67b74e2"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__macros.html#gae92890ad068051d74200a1ffb67b74e2">CY_SYSCLK_DRV_VERSION_MINOR</a>&#160;&#160;&#160;140</td></tr>
<tr class="memdesc:gae92890ad068051d74200a1ffb67b74e2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Driver minor version. <br /></td></tr>
<tr class="separator:gae92890ad068051d74200a1ffb67b74e2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7fbd2bd690d5954a03c6a09e1dd29530"><td class="memItemLeft" align="right" valign="top"><a id="ga7fbd2bd690d5954a03c6a09e1dd29530"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__macros.html#ga7fbd2bd690d5954a03c6a09e1dd29530">CY_SYSCLK_ID</a>&#160;&#160;&#160;<a class="el" href="group__group__syslib__macros__status__codes.html#ga45c44ce91d1e20c64430f00fd8ad9b0e">CY_PDL_DRV_ID</a>(0x12U)</td></tr>
<tr class="memdesc:ga7fbd2bd690d5954a03c6a09e1dd29530"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sysclk driver identifier. <br /></td></tr>
<tr class="separator:ga7fbd2bd690d5954a03c6a09e1dd29530"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab827d2ecd495fa4088417f3288c1c8e8"><td class="memItemLeft" align="right" valign="top"><a id="gab827d2ecd495fa4088417f3288c1c8e8"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__macros.html#gab827d2ecd495fa4088417f3288c1c8e8">CY_SYSCLK_ILO_FREQ</a>&#160;&#160;&#160;(32768UL)   /* Hz */</td></tr>
<tr class="memdesc:gab827d2ecd495fa4088417f3288c1c8e8"><td class="mdescLeft">&#160;</td><td class="mdescRight">ILO clock frequency. <br /></td></tr>
<tr class="separator:gab827d2ecd495fa4088417f3288c1c8e8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae9d92355d0cb0762745ad11bbed1084f"><td class="memItemLeft" align="right" valign="top"><a id="gae9d92355d0cb0762745ad11bbed1084f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__macros.html#gae9d92355d0cb0762745ad11bbed1084f">CY_SYSCLK_WCO_FREQ</a>&#160;&#160;&#160;(32768UL)   /* Hz */</td></tr>
<tr class="memdesc:gae9d92355d0cb0762745ad11bbed1084f"><td class="mdescLeft">&#160;</td><td class="mdescRight">WCO clock frequency. <br /></td></tr>
<tr class="separator:gae9d92355d0cb0762745ad11bbed1084f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaffa481a00710a6d6dea53ad1e12266c3"><td class="memItemLeft" align="right" valign="top"><a id="gaffa481a00710a6d6dea53ad1e12266c3"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__macros.html#gaffa481a00710a6d6dea53ad1e12266c3">CY_SYSCLK_PILO_FREQ</a>&#160;&#160;&#160;(32768UL)   /* Hz */</td></tr>
<tr class="memdesc:gaffa481a00710a6d6dea53ad1e12266c3"><td class="mdescLeft">&#160;</td><td class="mdescRight">PILO clock frequency. <br /></td></tr>
<tr class="separator:gaffa481a00710a6d6dea53ad1e12266c3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9b98d83b0a60b378966d56f7636d85a6"><td class="memItemLeft" align="right" valign="top"><a id="ga9b98d83b0a60b378966d56f7636d85a6"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__macros.html#ga9b98d83b0a60b378966d56f7636d85a6">CY_SYSCLK_IMO_FREQ</a>&#160;&#160;&#160;(8000000UL) /* Hz */</td></tr>
<tr class="memdesc:ga9b98d83b0a60b378966d56f7636d85a6"><td class="mdescLeft">&#160;</td><td class="mdescRight">IMO clock frequency. <br /></td></tr>
<tr class="separator:ga9b98d83b0a60b378966d56f7636d85a6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga40dbc1d4deedd96abbaf1790bb96cee2"><td class="memItemLeft" align="right" valign="top"><a id="ga40dbc1d4deedd96abbaf1790bb96cee2"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__macros.html#ga40dbc1d4deedd96abbaf1790bb96cee2">CY_SYSCLK_MFO_FREQ</a>&#160;&#160;&#160;(2000000UL) /* Hz */</td></tr>
<tr class="memdesc:ga40dbc1d4deedd96abbaf1790bb96cee2"><td class="mdescLeft">&#160;</td><td class="mdescRight">MFO clock frequency. <br /></td></tr>
<tr class="separator:ga40dbc1d4deedd96abbaf1790bb96cee2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa43941ffce9db407916a2d0da03dad47"><td class="memItemLeft" align="right" valign="top"><a id="gaa43941ffce9db407916a2d0da03dad47"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__macros.html#gaa43941ffce9db407916a2d0da03dad47">CY_SYSCLK_PILO_TRIM_STEP</a>&#160;&#160;&#160;(5UL) /* Default PILO TRIM Step size */</td></tr>
<tr class="memdesc:gaa43941ffce9db407916a2d0da03dad47"><td class="mdescLeft">&#160;</td><td class="mdescRight">CY_SYSCLK_PILO_TRIM_STEP is the default PILO TRIM Step value. <br /></td></tr>
<tr class="separator:gaa43941ffce9db407916a2d0da03dad47"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga45a41c9c03970ea3b6758f649abaa1ae"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__macros.html#ga45a41c9c03970ea3b6758f649abaa1ae">CY_SYSCLK_IHO_FREQ</a>&#160;&#160;&#160;(48000000UL) /* Hz */</td></tr>
<tr class="memdesc:ga45a41c9c03970ea3b6758f649abaa1ae"><td class="mdescLeft">&#160;</td><td class="mdescRight">IHO clock frequency.  <a href="#ga45a41c9c03970ea3b6758f649abaa1ae">More...</a><br /></td></tr>
<tr class="separator:ga45a41c9c03970ea3b6758f649abaa1ae"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga298156008f36e1fcec11a51efa2b71c9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__macros.html#ga298156008f36e1fcec11a51efa2b71c9">CY_SYSCLK_ECO_FREQ</a>&#160;&#160;&#160;(4000000UL) /* Hz */</td></tr>
<tr class="memdesc:ga298156008f36e1fcec11a51efa2b71c9"><td class="mdescLeft">&#160;</td><td class="mdescRight">ECO clock frequency.  <a href="#ga298156008f36e1fcec11a51efa2b71c9">More...</a><br /></td></tr>
<tr class="separator:ga298156008f36e1fcec11a51efa2b71c9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga45b6a9e242086c261e607b0438bda4bc"><td class="memItemLeft" align="right" valign="top"><a id="ga45b6a9e242086c261e607b0438bda4bc"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__macros.html#ga45b6a9e242086c261e607b0438bda4bc">CY_SYSCLK_BYPASS_CONFIGURE_DELAY</a>&#160;&#160;&#160;(2UL) /* micro seconds */</td></tr>
<tr class="memdesc:ga45b6a9e242086c261e607b0438bda4bc"><td class="mdescLeft">&#160;</td><td class="mdescRight">FLL BYPASS configure Delay , As per SAS "When changing BYPASS_SEL, do not turn off the reference clock
or CCO clock for ten cycles (whichever is slower)" Slower if IMO, so delay = (10 * 1/(IMO freq in Mhz)) = 1.25 micro seconds, approximated to 2 micro second. <br /></td></tr>
<tr class="separator:ga45b6a9e242086c261e607b0438bda4bc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad86b6fa733ec662fe862712b39939884"><td class="memItemLeft" align="right" valign="top"><a id="gad86b6fa733ec662fe862712b39939884"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__macros.html#gad86b6fa733ec662fe862712b39939884">CY_SYSCLK_FLL_DISABLE_TIMEOUT</a>&#160;&#160;&#160;(100UL) /* micro seconds */</td></tr>
<tr class="memdesc:gad86b6fa733ec662fe862712b39939884"><td class="mdescLeft">&#160;</td><td class="mdescRight">FLL Disable Timeout value. <br /></td></tr>
<tr class="separator:gad86b6fa733ec662fe862712b39939884"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6525bc3f18734ac37a14c7f4ca14093a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__sysclk__macros.html#ga6525bc3f18734ac37a14c7f4ca14093a">CY_SYSCLK_IS_CLKPATH_SOURCE_VALID</a>(clkSrc)</td></tr>
<tr class="separator:ga6525bc3f18734ac37a14c7f4ca14093a"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a id="ga45a41c9c03970ea3b6758f649abaa1ae"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga45a41c9c03970ea3b6758f649abaa1ae">&#9670;&nbsp;</a></span>CY_SYSCLK_IHO_FREQ</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
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          <td class="memname">#define CY_SYSCLK_IHO_FREQ&#160;&#160;&#160;(48000000UL) /* Hz */</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>IHO clock frequency. </p>
<dl class="section note"><dt>Note</dt><dd>This macro is available for CAT1B devices. </dd></dl>

</div>
</div>
<a id="ga298156008f36e1fcec11a51efa2b71c9"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga298156008f36e1fcec11a51efa2b71c9">&#9670;&nbsp;</a></span>CY_SYSCLK_ECO_FREQ</h2>

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          <td class="memname">#define CY_SYSCLK_ECO_FREQ&#160;&#160;&#160;(4000000UL) /* Hz */</td>
        </tr>
      </table>
</div><div class="memdoc">

<p>ECO clock frequency. </p>
<dl class="section note"><dt>Note</dt><dd>This macro is available for CAT1A devices. </dd></dl>

</div>
</div>
<a id="ga6525bc3f18734ac37a14c7f4ca14093a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga6525bc3f18734ac37a14c7f4ca14093a">&#9670;&nbsp;</a></span>CY_SYSCLK_IS_CLKPATH_SOURCE_VALID</h2>

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          <td class="memname">#define CY_SYSCLK_IS_CLKPATH_SOURCE_VALID</td>
          <td>(</td>
          <td class="paramtype">&#160;</td>
          <td class="paramname">clkSrc</td><td>)</td>
          <td></td>
        </tr>
      </table>
</div><div class="memdoc">
<b>Value:</b><div class="fragment"><div class="line">(((clkSrc) == <a class="code" href="group__group__sysclk__path__src__enums.html#gga8ddaf9023a02dee0d1f9a5629d6ccfe6a01c7cbab413a99daa41d2fb7a0340955">CY_SYSCLK_CLKPATH_IN_IMO</a>) || \</div><div class="line">                                                         ((clkSrc) == <a class="code" href="group__group__sysclk__path__src__enums.html#gga8ddaf9023a02dee0d1f9a5629d6ccfe6aca51f919d42d3b386f0c631768916c16">CY_SYSCLK_CLKPATH_IN_EXT</a>)  || \</div><div class="line">                                                         ((clkSrc) == <a class="code" href="group__group__sysclk__path__src__enums.html#gga8ddaf9023a02dee0d1f9a5629d6ccfe6a28f5ad80fd20d8459d40aa8b86d3a77e">CY_SYSCLK_CLKPATH_IN_ECO</a>) || \</div><div class="line">                                                         ((clkSrc) == <a class="code" href="group__group__sysclk__path__src__enums.html#gga8ddaf9023a02dee0d1f9a5629d6ccfe6ab4d13855682d5b3296f7e57eb3581b40">CY_SYSCLK_CLKPATH_IN_ILO0</a>)  || \</div><div class="line">                                                         ((clkSrc) == <a class="code" href="group__group__sysclk__path__src__enums.html#gga8ddaf9023a02dee0d1f9a5629d6ccfe6a17e0425e3a65a38ca77b18ae7528bc72">CY_SYSCLK_CLKPATH_IN_WCO</a>) || \</div><div class="line">                                                         ((clkSrc) == <a class="code" href="group__group__sysclk__path__src__enums.html#gga8ddaf9023a02dee0d1f9a5629d6ccfe6a92cec13a6997817a985c9dae7460f0fe">CY_SYSCLK_CLKPATH_IN_ILO1</a>))</div><div class="ttc" id="group__group__sysclk__path__src__enums_html_gga8ddaf9023a02dee0d1f9a5629d6ccfe6a28f5ad80fd20d8459d40aa8b86d3a77e"><div class="ttname"><a href="group__group__sysclk__path__src__enums.html#gga8ddaf9023a02dee0d1f9a5629d6ccfe6a28f5ad80fd20d8459d40aa8b86d3a77e">CY_SYSCLK_CLKPATH_IN_ECO</a></div><div class="ttdoc">Select the ECO as the output of the path mux. </div><div class="ttdef"><b>Definition:</b> cy_sysclk.h:1985</div></div>
<div class="ttc" id="group__group__sysclk__path__src__enums_html_gga8ddaf9023a02dee0d1f9a5629d6ccfe6a92cec13a6997817a985c9dae7460f0fe"><div class="ttname"><a href="group__group__sysclk__path__src__enums.html#gga8ddaf9023a02dee0d1f9a5629d6ccfe6a92cec13a6997817a985c9dae7460f0fe">CY_SYSCLK_CLKPATH_IN_ILO1</a></div><div class="ttdoc">Select the ILO1 (20) as the output of the DSI mux and path mux. </div><div class="ttdef"><b>Definition:</b> cy_sysclk.h:2002</div></div>
<div class="ttc" id="group__group__sysclk__path__src__enums_html_gga8ddaf9023a02dee0d1f9a5629d6ccfe6aca51f919d42d3b386f0c631768916c16"><div class="ttname"><a href="group__group__sysclk__path__src__enums.html#gga8ddaf9023a02dee0d1f9a5629d6ccfe6aca51f919d42d3b386f0c631768916c16">CY_SYSCLK_CLKPATH_IN_EXT</a></div><div class="ttdoc">Select the EXT as the output of the path mux. </div><div class="ttdef"><b>Definition:</b> cy_sysclk.h:1984</div></div>
<div class="ttc" id="group__group__sysclk__path__src__enums_html_gga8ddaf9023a02dee0d1f9a5629d6ccfe6a01c7cbab413a99daa41d2fb7a0340955"><div class="ttname"><a href="group__group__sysclk__path__src__enums.html#gga8ddaf9023a02dee0d1f9a5629d6ccfe6a01c7cbab413a99daa41d2fb7a0340955">CY_SYSCLK_CLKPATH_IN_IMO</a></div><div class="ttdoc">Select the IMO as the output of the path mux. </div><div class="ttdef"><b>Definition:</b> cy_sysclk.h:1986</div></div>
<div class="ttc" id="group__group__sysclk__path__src__enums_html_gga8ddaf9023a02dee0d1f9a5629d6ccfe6a17e0425e3a65a38ca77b18ae7528bc72"><div class="ttname"><a href="group__group__sysclk__path__src__enums.html#gga8ddaf9023a02dee0d1f9a5629d6ccfe6a17e0425e3a65a38ca77b18ae7528bc72">CY_SYSCLK_CLKPATH_IN_WCO</a></div><div class="ttdoc">Select the WCO (17) as the output of the DSI mux and path mux. </div><div class="ttdef"><b>Definition:</b> cy_sysclk.h:1996</div></div>
<div class="ttc" id="group__group__sysclk__path__src__enums_html_gga8ddaf9023a02dee0d1f9a5629d6ccfe6ab4d13855682d5b3296f7e57eb3581b40"><div class="ttname"><a href="group__group__sysclk__path__src__enums.html#gga8ddaf9023a02dee0d1f9a5629d6ccfe6ab4d13855682d5b3296f7e57eb3581b40">CY_SYSCLK_CLKPATH_IN_ILO0</a></div><div class="ttdoc">Select the ILO0 (16) as the output of the DSI mux and path mux. </div><div class="ttdef"><b>Definition:</b> cy_sysclk.h:1995</div></div>
</div><!-- fragment --><dl class="section note"><dt>Note</dt><dd>This macro is valid for CAT1A (TVIIBE only) and CAT1C devices. </dd></dl>

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